Bandgap voltage reference circuits are well known in the art. Such circuits are designed to sum two voltages with opposite temperature slopes. One of the voltages is a Complementary-To-Absolute Temperature (CTAT) voltage typically provided by a base-emitter voltage of a forward biased bipolar transistor. The other is a Proportional-To-Absolute Temperature (PTAT) voltage typically derived from the base-emitter voltage differences of two bipolar transistors operating at different collector current densities. When the PTAT voltage and the CTAT voltage are summed together the summed voltage is at a first order temperature insensitive.
An example of a prior art bandgap voltage reference 100 is illustrated in FIG. 1. Such a circuit is typical of prior art arrangements and requires two resistors. The bandgap voltage reference circuit 100 includes a first substrate PNP bipolar transistor Q1 operating at a first collector current density and a second substrate PNP bipolar transistor Q2 operating at a second collector current density which is less than that of the first collector current density. The emitter of the first bipolar transistor Q1 is coupled to the inverting input of an operational amplifier A and the emitter of the second bipolar transistor Q2 is coupled via a resistor r1 to the non-inverting input of the amplifier A. The collector current density difference between Q1 and Q2 may be established by having the emitter area of the second bipolar transistor Q2 larger than the emitter area of the first bipolar transistor Q1. Alternatively multiple transistors may be provided in each leg, with the sum of the collector currents of each of the transistors in a first leg being greater than that in a second leg. As a consequence of the differences in collector current densities between the bipolar transistors Q1 and Q2 a base-emitter voltage difference (ΔVbe) is developed across the resistor r1.
                              Δ          ⁢                                          ⁢                      V            be                          =                              kT            q                    ⁢                      ln            ⁡                          (              n              )                                                          (        1        )            
Where:                k is the Boltzmann constant,        q is the charge on the electron,        T is the operating temperature in Kelvin,        n is the collector current density ratio of the two bipolar transistors.        
A PTAT current, IPTAT, is generated as a result of the voltage difference ΔVbe dropped across r1.
                              I          PTAT                =                              Δ            ⁢                                                  ⁢                          V              be                                            r            1                                              (        2        )            
A current mirror arrangement comprising three PMOS transistors MP1, MP2 and MP3 of similar or different aspect ratios are driven by the output of the amplifier A to mirror the PTAT current IPTAT. It will be appreciated by those skilled in the art that the collector current density difference between Q1 and Q2 can also be achieved by having the aspect ratio (related to the Width/Length (W/L) of the MOS device) of MP1 greater than the aspect ratio (W/L) of MP2 so that the drain current of MP1 is greater than the drain current of MP2.
A third PNP bipolar transistor Q3 is coupled to a voltage reference output node ref via a resistor r2. The PMOS transistor MP3 mirrors the PTAT current IPTAT derived from the emitter voltage difference (ΔVbe) developed across the resistor r1. The PTAT current provided by MP3 flows to the emitter of the third bipolar transistor Q3 through resistor r2. The voltage at the output node ref is equal to the summation of the base emitter voltage Vbe of the third bipolar transistor Q3 plus the base emitter voltage difference ΔVbe resulting from the PTAT current IPTAT flowing through r2.
                              V          ref                =                                                            V                be                            ⁡                              (                                  Q                  ⁢                                                                          ⁢                  3                                )                                      +                                          I                PTAT                            *                              r                2                                              =                                                    V                be                            ⁡                              (                                  Q                  ⁢                                                                          ⁢                  3                                )                                      +                          Δ              ⁢                                                          ⁢                              V                be                            *                                                r                  2                                                  r                  1                                                                                        (        3        )            
Accordingly, the voltage reference Vref at node ref is dependent on the resistance of resistors r1 and r2. For a specific current density ratio, n, and a corresponding resistor ratio, r2/r1, the reference voltage is substantially temperature insensitive.
It will be understood that when providing circuits in silicon that different circuit elements will occupy different amounts of the available silicon substrate. For low power applications resistors typically occupy relative large areas. From a review of FIG. 1, it is apparent that the bandgap voltage reference circuit 100 requires two resistors r1, r2. These elements will occupy a large silicon area which is undesirable for low power voltage designs.
As well as occupying large areas on the silicon, those skilled in the art will appreciate that resistors suffer in their sensitivity to process variations in that the resistance of resistors may vary from lot to lot of the order of +/−20%. Such resistance variation of the resistors r1 and r2 results in a corresponding PTAT current IPTAT variation and hence a reference voltage Vref variation.
There is therefore a need to provide a bandgap voltage reference which may be implemented using a reduced silicon area than for prior art arrangements. Such a reference could be used for low power applications and should exhibit less sensitivity to process variation.